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vCMP logical interfaces throughput
- Feb 10, 2023
The hypervisor is virtualizing networking so you will see an 'interface' for each vCPU.
For standard VS's , typically a TMM can't process more then 10G of traffic, for fastl4 use cases the FPGA offload occurs before TMM.
Said another way, there isn't a hard cap on bandwidth to the guest but there are practical limits in place for most traffic use cases.
https://support.f5.com/csp/article/K03740927
The hypervisor is virtualizing networking so you will see an 'interface' for each vCPU.
For standard VS's , typically a TMM can't process more then 10G of traffic, for fastl4 use cases the FPGA offload occurs before TMM.
Said another way, there isn't a hard cap on bandwidth to the guest but there are practical limits in place for most traffic use cases.
https://support.f5.com/csp/article/K03740927
Thak you Brian_Van_Lieu for the answer and article suggestion.
"Said another way, there isn't a hard cap on bandwidth to the guest but there are practical limits in place for most traffic use cases. " In essence are the limits of processing per vcmp and the type of traffic/layer going trough rigth ?
"typically a TMM can't process more then 10G of traffic" Can i undertand that a single vcmp even with 8vCPUs cant process more that 10G of traffic?
- Brian_Van_LieuFeb 15, 2023Employee
TMM is threaded on the cores, so its really 10G/s (or more) per TMM. The 10G/s per TMM is a round-ish number for guidance, not an absolute.
If you have 4 TMMs, you can achieve 40Gb/s (or more).
This is very dependent of course on traffic, packet sizes, and what additional (if any) work BIG-IP is doing on the traffic as it passes through the data plane.
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